Points to Ponder : 

1) About Fig.6-13. The Decode format for a microinstruction address.
The Microstore contains 2048 microcodewords, each of size 41 bits. 
2048 being 2^11, each such microcodeword has a 11-bit address. 
Fig. 6-13 shows how the control unit decodes from the fetched 
instruction. What does decoding refer to, here? It just means, that
the control store gets to know from the fetched instruction in the IR,
where exactly the microcode implementing this particular instruction
lies, in the microcode store. So, essentially, decoding means to get
a 11-bit address from the fetched instruction, namely the 11-bit address
of the starting point of where the microcode for this instruction lies 
in the microcode store. 
Fig.6-13 shows that the first bit (the MSB) of the (starting microcode)
address for a fetched instruction is always 1, and the last two bits are 
0. About the last two bits, them being zero means, that the generated 
addresses are always multiples of 4. Which is a nice bit of uniformity 
to have. Is it just uniformity? well, actually no. What we are doing is 
allowing enough space to implement each instruction that we have. We
are being pragmatic, and allowing 4 microcodewords for each instruction.
Observe, in Fig.6-15, most of the operations/instructions, for instance,
call, addcc, ... are 4 microcodewords long each, except for "st".
But, what about the starting bit being always 1. That means, 
for instance, that for any fetched instruction, the microcode lies 
beyond address 1024 in the micro control store. So, what about all 
the space in the MCS before 1024 ?

2) Another point. The latter part of (1) above shows that the microcode
for any fetched instruction lies beyond address 1024 in the micro 
control store. There are a lot of instructions, and just 1024 addresses to fit 
them all in? What happens if we want to implement new instructions, do we 
have space enough to fit in more microcode for them ?
Observe the form of the MCS address generated for a fetched instruction,
again, from Fig.6-13. The op comes before the op3 (from left to right, 
i.e.) which shows, that similar operations are grouped together in the MCS, as 
compared to dissimilar operations. That seems logical enough. What do we 
mean by similar operations? The obvious thing, that is, operations whose 
op codes are the same. For instance, the arithmetic operations, on the 
one and have opcode 10, whereas the Memory operations have opcode 11.
So, the addresses [whenever we refer to addresses in this note, it 
refers to addresses in the MCS, the microcode control store] for the arithmetic
operations start out like : 
1 1 0 * * * * * * 0 0
whereas for the memory operations, the addresses are of the form : 
1 1 1 * * * * * * 0 0 

So, the space (in the MCS) that we have for implementing the arithmetic 
operations, using microcode, is about : (all the computation being in 
binary)
1 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0, that is, about 2^9 or 512 
codewords.
This suffices for all the arithmetic instructions.